#ifndef FPGA_DRV_H
#define FPGA_DRV_H

#include "../global/ObasicTypes.h"
#include <vector>
#include <map>
#include <pthread.h>
#include <linux/input.h>


#define OUTPUT_LEDNET 1


//#define  FPGA_MASTER_NEAR_VBYEON        1           //将靠近VBYONE的FPGA进行编号标记
//#define  FPGA_SLAVER_NEAR_OUTMINTOR     0           //将靠近预监的FPGA进行编号
typedef enum {
    //G32 type
    FPGA_FLASH_VBYONE2 = 0x03,
    FPGA_FLASH_VBYONE1 = 0X02,
    FPGA_MASTER_VBYONE1 = 0x00,
    FPGA_MASTER_VBYONE2 = 0x01,
    C331_FONT_FLASH = 0x04,
    SOURCE_CHIP_FLASH = 0x08,

} ONBON_OVP_FPGA_MASTER_VBYONE_INDEX;





#define   FPGA_CMD_EN_RD       1
#define   FPGA_CMD_EN_WR       0


typedef enum {
    FPGA_CMD_SEL_FLASH = 0,
    FPGA_CMD_SEL_RAM = 1,
    FPGA_CMD_SEL_REG = 2
} ONBON_FPGA_CMD_SEL;



//
#define RAM_MAX_LEN                      (1024)
#define FPGA_RAM_MAX_LEN		 (1024)	//!<RAM数组大小
#define REG_MAX_NUM		        (0xaa)	//!<RAM数组大小
#define FPGA_RAM_DEFAULT_LEN     2048

#define MCU_RAM_ETH_LEN             (8+128)//16*8(LCD w,LCDy)

#define  BRI_TASK_CHECK_TIME  1000   //每10秒钟检查1次
#define BRIGHTNESS_TIME       30    //默认亮度调正时间


typedef enum{

    FPGA_RAM_REG_02 =(0x02),
    FPGA_STATE_REG_03 = (0x03),
    FPGA_BRIGHT_REG_06 = (0x06),
    FPGA_HARD_PCB_VERSION = (0X07),
    FPGA_JUMP_REG = (0x15),         //about jump
    FPGA_STATE0_REG = (0x16),       //FPGA status reg
    FPGA_CLEAR_REG = (0x17),        //FPGA clear reg
    RX_RAM_LOW_REG_12 = (0x18),     //网口 1,2 的 RX_RAM 内部有效数据长度----低字节部分
    RX_RAM_LOW_REG =(0x18),         //RX_RAM内部有效数据长度--低字节部分
    RX_RAM_HIGH_REG = (0x19),      //RX_RAM内部有效数据长度--高字节部分
    TX_RAM_LOW_REG =  (0x1A),      //TX_RAM内部有效数据长度--低字节部分
    TX_RAM_LOW_REG_12 = (0x1A),    //网口 1,2 的 TX_RAM 内部有效数据长度----低字节部分
    TX_RAM_HIGH_REG =  (0x1B),     //TX_RAM内部有效数据长度--高字节部分
    FPGA_BYTE0_REG = (0x1C),       //FPGA版本号--BYTE0
    FPGA_BYTE1_REG = (0x1D),       //FPGA版本号--BYTE1
    FPGA_BYTE2_REG = (0x1E),       //FPGA版本号--BYTE2
    FPGA_BYTE3_REG = (0x1F),       //FPGA版本号--BYTE3
    FPGA_UID0_REG = (0x20),
    FPGA_UID1_REG = (0x21),
    FPGA_UID2_REG = (0x22),
    FPGA_UID3_REG = (0x23),
    FPGA_UID4_REG = (0x24),
    FPGA_UID5_REG = (0x25),
    FPGA_UID6_REG = (0x26),
    FPGA_UID7_REG = (0x27),
    FPGA_VBO_REG = (0x28),
    FPGA_ALIGN_REG = (0x29),
    FPGA_TX_ERROR_REG = (0x2A),
    FPGA_VBY_LOCK_ERROR_REG = (0x2B),
    FPGA_INIT_OK = (0x50),          //FPGA启动后，是否正常初始化标记(01正常 02异常)

    FPGA_STATE1_REG = (0x80) ,      //FPGA状态寄存器1
    FPGA_STATE2_REG = (0x81),       //FPGA状态寄存器2
    FPGA_CLEAR1_REG = (0x82) ,      //FPGA清除寄存器1
    FPGA_CONTROL1_REG = (0x83) ,    //FPGA控制寄存器1
    FPGA_CONTROL2_REG = (0x84),     //FPGA控制寄存器2
    RX_RAM_LOW_REG_34 = (0x85) ,    //网口 3,4 的 RX_RAM 内部有效数据长度----低字节部分
    TX_RAM_LOW_REG_34 = (0x86) ,    //网口 3,4 的 TX_RAM 内部有效数据长度----低字节部分
    RX_RAM_LOW_REG_56 = (0x87) ,    //网口 5,6 的 RX_RAM 内部有效数据长度----低字节部分
    TX_RAM_LOW_REG_56 = (0x88) ,    //网口 5,6 的 TX_RAM 内部有效数据长度----低字节部分
    RX_RAM_LOW_REG_78 = (0x89) ,    //网口 7,8 的 RX_RAM 内部有效数据长度----低字节部分
    TX_RAM_LOW_REG_78 = (0x8A) ,    //网口 7,8 的 TX_RAM 内部有效数据长度----低字节部分

    FPGA_STATE3_REG = (0x90) ,      //FPGA状态寄存器3
    FPGA_STATE4_REG = (0x91) ,      //FPGA状态寄存器4
    FPGA_CLEAR2_REG = (0x92) ,      //FPGA清除寄存器2
    FPGA_CONTROL3_REG = (0x93) ,    //FPGA控制寄存器3
    FPGA_CONTROL4_REG = (0x94),     //FPGA控制寄存器4
    RX_RAM_LOW_REG_910 = (0x95) ,    //网口 9,10 的 RX_RAM 内部有效数据长度----低字节部分
    RX_RAM_LOW_REG_1112 = (0x96) ,    //网口 11,12 的 RX_RAM 内部有效数据长度----低字节部分
    RX_RAM_LOW_REG_1314 = (0x97) ,    //网口 13,14 的 RX_RAM 内部有效数据长度----低字节部分
    RX_RAM_LOW_REG_1516 = (0x98) ,    //网口 15,16 的 RX_RAM 内部有效数据长度----低字节部分
    RX_RAM_HIGH_REG2 = (0x99) ,     //RX_RAM网口 9~16 内部有效数据长度--高字节部分
    TX_RAM_LOW_REG_910 = (0x9A) ,    //网口 9,10 的 TX_RAM 内部有效数据长度----低字节部分
    TX_RAM_LOW_REG_1112 = (0x9B) ,    //网口 11,12 的 TX_RAM 内部有效数据长度----低字节部分
    TX_RAM_LOW_REG_1314 = (0x9C) ,    //网口 13,14 的 TX_RAM 内部有效数据长度----低字节部分
    TX_RAM_LOW_REG_1516 = (0x9D) ,    //网口 15,16 的 TX_RAM 内部有效数据长度----低字节部分
    TX_RAM_HIGH_REG2 =  (0x9E),     //TX_RAM网口 9~16 内部有效数据长度--高字节部分

} ONBON_FPGA_REG_RAM_ADDR;
//




//fpga netport ram
//can delet write to reg_ram_addr
typedef enum{
#if 0
    RX_RAM_12 = 1,                     //net1,2 ram_rcv
    TX_RAM_12 = 2,                     //net1,2 ram_tx
    RX_RAM_34 = 3,                     //net3,4 ram_rcv
    TX_RAM_34 = 4,                     //net3,4 ram_tx
    RX_RAM_56 = 5,                     //net5,6 ram_rcv
    TX_RAM_56 = 6,                     //net5,6 ram_tx
    RX_RAM_78 = 7,                     //net7,8 ram_rcv
    TX_RAM_78 = 8,                     //net7,8 ram_tx
#else
    /************FPGA 与 MCU 共同的参数 RAM 地址**************/
    PARA_RAM = 1,
    /************FPGA  内部网口的 RX_TX_RAM 地址**************/
    RX_RAM_12 = 2,                     //net1,2 ram_rcv
    TX_RAM_12 = 3,                     //net1,2 ram_tx

    RX_RAM_34 = 4,                     //net3,4 ram_rcv
    TX_RAM_34 = 5,                     //net3,4 ram_tx

    RX_RAM_56 = 6,                     //net5,6 ram_rcv
    TX_RAM_56 = 7,                     //net5,6 ram_tx

    RX_RAM_78 = 8,                     //net7,8 ram_rcv
    TX_RAM_78 = 9,                     //net7,8 ram_tx

    RX_RAM_910 = 10,                     //net9,10 ram_rcv
    TX_RAM_910 = 11,                     //net9,10 ram_tx

    RX_RAM_1112 = 12,                     //net11,12 ram_rcv
    TX_RAM_1112 = 13,                     //net11,12 ram_tx

    RX_RAM_1314 = 14,                     //net13,14 ram_rcv
    TX_RAM_1314 = 15,                     //net13,14 ram_tx

    RX_RAM_1516 = 16,                     //net15,16 ram_rcv
    TX_RAM_1516 = 17,                     //net15,16 ram_tx
    /************FPGA 内部保留的 RAM 地址**************/
    RECEIVED_RAM = 33,
    /************FPGA 内部的缩放 RAM 地址**************/
    LCD0_RAM_H = 34,
    LCD0_RAM_W = 35,

    LCD1_RAM_H = 36,
    LCD1_RAM_W = 37,

    LCD2_RAM_H = 38,
    LCD2_RAM_W = 39,

    LCD3_RAM_H = 40,
    LCD3_RAM_W = 41,

    LCD4_RAM_H = 42,
    LCD4_RAM_W = 43,

    LCD5_RAM_H = 44,
    LCD5_RAM_W = 45,

    LCD6_RAM_H = 46,
    LCD6_RAM_W = 47,

    LCD7_RAM_H = 48,
    LCD7_RAM_W = 49,
    /************FPGA 内部校验的 RAM 地址**************/
    CRC_RAM = 50
#endif
} ONBON_FPGA_RX_TX_RAM_;






//ent port ram
typedef enum{
    ETH0_X = 0x08,
    ETH0_Y = 0x0A,
    ETH0_W = 0x0C,
    ETH0_H = 0x0E,
    ETH1_X = 0x13,
    ETH1_Y = 0x15,
    ETH1_W = 0x17,
    ETH1_H = 0x19,
    ETH2_X = 0x20,
    ETH2_Y = 0x22,
    ETH2_W = 0x24,
    ETH2_H = 0x26,
    ETH3_X = 0x2B,
    ETH3_Y = 0x2D,
    ETH3_W = 0x2F,
    ETH3_H = 0x31,
    ETH4_X = 0x208,
    ETH4_Y = 0x20A,
    ETH4_W = 0x20C,
    ETH4_H = 0x20E,
    ETH5_X = 0x210,
    ETH5_Y = 0x212,
    ETH5_W = 0x214,
    ETH5_H = 0x216,
    ETH6_X = 0x218,
    ETH6_Y = 0x21A,
    ETH6_W = 0x21C,
    ETH6_H = 0x21E,
    ETH7_X = 0x220,
    ETH7_Y = 0x222,
    ETH7_W = 0x224,
    ETH7_H = 0x226,

    ETH8_X = 0x240,
    ETH8_Y = 0x242,
    ETH8_W = 0x244,
    ETH8_H = 0x246,
    ETH9_X = 0x248,
    ETH9_Y = 0x24A,
    ETH9_W = 0x24C,
    ETH9_H = 0x24E,
    ETH10_X = 0x250,
    ETH10_Y = 0x252,
    ETH10_W = 0x254,
    ETH10_H = 0x256,
    ETH11_X = 0x258,
    ETH11_Y = 0x25A,
    ETH11_W = 0x25C,
    ETH11_H = 0x25E,
    ETH12_X = 0x260,
    ETH12_Y = 0x262,
    ETH12_W = 0x264,
    ETH12_H = 0x266,
    ETH13_X = 0x268,
    ETH13_Y = 0x26A,
    ETH13_W = 0x26C,
    ETH13_H = 0x26E,
    ETH14_X = 0x270,
    ETH14_Y = 0x272,
    ETH14_W = 0x274,
    ETH14_H = 0x276,
    ETH15_X = 0x278,
    ETH15_Y = 0x27A,
    ETH15_W = 0x27C,
    ETH15_H = 0x27E,

    ETH_LCD_X = 0x38,
    ETH_LCD_Y = 0x3a,
    ETH_LCD_W  = 0x3C,
    ETH_LCD_H = 0x3E,

    //
    ETH_PORT1_ID = 0x114,
    ETH_PORT2_ID = 0x115,
    ETH_PORT3_ID = 0x116,
    ETH_PORT4_ID = 0x117,
    ETH_PORT5_ID = 0x118,
    ETH_PORT6_ID = 0x119,
    ETH_PORT7_ID = 0x11a,
    ETH_PORT8_ID = 0x11b,
    ETH_PORT9_ID = 0x11c,
    ETH_PORT10_ID = 0x11d,
    ETH_PORT11_ID = 0x11e,
    ETH_PORT12_ID = 0x11f,
    ETH_PORT13_ID = 0x120,
    ETH_PORT14_ID = 0x121,
    ETH_PORT15_ID = 0x122,
    ETH_PORT16_ID = 0x123,

    ETH0_FRAME_SIZE = 0x128,
    ETH15_PIX_INC = 0x166,

    DIV_W   = 0x74,

    //about lcd x_y
    LCD_VBY_X = 0x1F0,//just for G32
    LCD_VBY_Y = 0x1F2

} ONBON_ETH_ADDR_PARA;



//back eth para
typedef enum{
    MCU_BACK_ETH_LCD_X = 0x84,
    MCU_BAKC_ETH_LCD_Y = 0X86,
    MCU_BACK_ETH_LCD_W = 0x00,
    MCU_BACK_ETH_LCD_H = 0x02,
    MCU_BACK_ETH0_X = 0x04,
    MCU_BACK_ETH0_Y = 0x06,
    MCU_BACK_ETH0_W = 0x08,
    MCU_BACK_ETH0_H = 0x0A,
    MCU_BACK_ETH1_X = 0x0C,
    MCU_BACK_ETH1_Y = 0x0E,
    MCU_BACK_ETH1_W = 0x10,
    MCU_BACK_ETH1_H = 0x12,
    MCU_BACK_ETH2_X = 0x14,
    MCU_BACK_ETH2_Y = 0x16,
    MCU_BACK_ETH2_W = 0x18,
    MCU_BACK_ETH2_H = 0x1A,
    MCU_BACK_ETH3_X = 0x1C,
    MCU_BACK_ETH3_Y = 0x1E,
    MCU_BACK_ETH3_W = 0x20,
    MCU_BACK_ETH3_H = 0x22,
    MCU_BACK_ETH4_X = 0x24,
    MCU_BACK_ETH4_Y = 0x26,
    MCU_BACK_ETH4_W = 0x28,
    MCU_BACK_ETH4_H = 0x2A,
    MCU_BACK_ETH5_X = 0x2C,
    MCU_BACK_ETH5_Y = 0x2E,
    MCU_BACK_ETH5_W = 0x30,
    MCU_BACK_ETH5_H = 0x32,
    MCU_BACK_ETH6_X = 0x34,
    MCU_BACK_ETH6_Y = 0x36,
    MCU_BACK_ETH6_W = 0x38,
    MCU_BACK_ETH6_H = 0x3A,
    MCU_BACK_ETH7_X = 0x3C,
    MCU_BACK_ETH7_Y = 0x3E,
    MCU_BACK_ETH7_W = 0x40,
    MCU_BACK_ETH7_H = 0x42,

    MCU_BACK_ETH8_X = 0x44,
    MCU_BACK_ETH8_Y = 0x46,
    MCU_BACK_ETH8_W = 0x48,
    MCU_BACK_ETH8_H = 0x4A,
    MCU_BACK_ETH9_X = 0x4C,
    MCU_BACK_ETH9_Y = 0x4E,
    MCU_BACK_ETH9_W = 0x50,
    MCU_BACK_ETH9_H = 0x52,
    MCU_BACK_ETH10_X = 0x54,
    MCU_BACK_ETH10_Y = 0x56,
    MCU_BACK_ETH10_W = 0x58,
    MCU_BACK_ETH10_H = 0x5A,
    MCU_BACK_ETH11_X = 0x5C,
    MCU_BACK_ETH11_Y = 0x5E,
    MCU_BACK_ETH11_W = 0x60,
    MCU_BACK_ETH11_H = 0x62,
    MCU_BACK_ETH12_X = 0x64,
    MCU_BACK_ETH12_Y = 0x66,
    MCU_BACK_ETH12_W = 0x68,
    MCU_BACK_ETH12_H = 0x6A,
    MCU_BACK_ETH13_X = 0x6C,
    MCU_BACK_ETH13_Y = 0x6E,
    MCU_BACK_ETH13_W = 0x70,
    MCU_BACK_ETH13_H = 0x72,
    MCU_BACK_ETH14_X = 0x74,
    MCU_BACK_ETH14_Y = 0x76,
    MCU_BACK_ETH14_W = 0x78,
    MCU_BACK_ETH14_H = 0x7A,
    MCU_BACK_ETH15_X = 0x7C,
    MCU_BACK_ETH15_Y = 0x7E,
    MCU_BACK_ETH15_W = 0x80,
    MCU_BACK_ETH15_H = 0x82


} ONBON_MCU_BACK_ETH_ADDR_PARA;


class fpga_drv
{
public:
    fpga_drv() ;
    ~fpga_drv() ;

    int initialize_vbyne1(Ouint8 sel);
//    int get_fpga_irq_fd(Ouint8 sel) ;
//    void close_fpga_irq_fd(int fd) ;

    int SPI_Transfer(int fd, const unsigned char *TxBuf, unsigned char *RxBuf, Ouint32 len);
    int SPI_Transfer_Write(int fd, const unsigned char *TxBuf,Ouint32 len);

    void FPGA_SPI_Disable_WP(int fd);
    void FPGA_SPI_WAIT_BUSY(int fd) ;
    Ouint8 FPGA_SPI_FLASH_VBYONE_ERASE(Ouint8 name,Ouint32 sec, Ouint8 mode,Ouint32 num) ;
    Ouint8 FPGA_SPI_FLASH_VBYONE_WRITE(Ouint8 name,Ouint32 Dst,Ouint8* SndbufPt,Ouint32 NByte) ;
    Ouint8 FPGA_SPI_FLASH_VBYONE_READ(Ouint8 name,Ouint32 Dst,Ouint32 NByte,Ouint8* RcvBufPt) ;

    void FPGA_SPI_FLASH_SSTF016B_RD_UID(Ouint8 name ,Ouint8* buf) ;

//    int SPI_Write(int fd ,unsigned char *TxBuf, int len) ;
//    int SPI_Read(int fd ,unsigned char *RxBuf, int len) ;

//    void read_fpga_register(uint32 reg, uint8 *value,uint8 sel_fpag) ;
//    uint16 fpga_cmd_to_spi_data(uint32 ram_flash_sel, uint32 start_addr, uint32 wr_rd) ;


//    void read_from_register(uint8 reg_addr,uint8 sel_fpag) ;
//    void write_to_register(uint8 reg_addr,uint8 reg_mask,uint8 reg_data,uint8 sel_fpag) ;



private:
    //int G_CURRENTBNK;
    //unsigned int G_BUFCNT;
};




#endif // FPGA_DRV_H
